Before logic synthesis, STAR enables full implementation capabilities towards IP and connectivity insertion with a real-time monitoring of the integration progress. This enables SoC creation in minutes and maximize design reuse from existing projects.
Benefits
- Get up to 90% of design reuse and higher including RTL and design collaterals
- Enables SoC creation even if design blocks and views are missing
- Reduce drastically TAT and engineering effort
Features
- Multi-format IP cores and connectivity insertion including IP-XACT 2009 and IP-XACT 2014
- Physically and Power aware integration process at RTL
- Monitor SoC integration progress real-time
- Generate full chip views including RTL, IP-XACT, UPF and SDC
- RTL Design Editing
- UPF automatic generation
- Core Wrapping at RTL
Other Related Solutions
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