After three years of a collaborative R&D work between CEA, Defacto Technologies, and Innova Advanced Technologies, SoC PLANNER platform is now available for early-adopters. The platform introduces an automated front-end design flow that bridges architecture specification, Design Space Exploration, workflow orchestration and RTL generation within a single environment, while integrating sustainability metrics throughout the exploration process.
Grenoble, France - [2026, September 8] CEA, Defacto Technologies, and Innova Advanced Technologies today announced the completion of SoC PLANNER, a three-years project funded by BPI France, as part of the France 2030 program, and aiming to develop next-generation System-on-Chip (SoC) design exploration platform. SoC PLANNER is now ready for early adopters.
With over a trillion chips manufactured every year and application requirements evolving faster than ever, across automotive, HPC, and AI, the pressure on SoC design teams has never been higher. For a complex SoC project, the number of possible configurations to evaluate can reach into the millions, with parameters deeply interdependent and objectives (power, performance, area, time-to-market) fundamentally in tension. Manual or semi-manual design exploration, even when supported by experienced architects, remains highly complex and unsustainable. SoC PLANNER provides full automation and addresses such challenges.
A Fully Integrated, Automated Design Flow
SoC PLANNER combines three complementary technologies developed by the project partners:
- CEA's A-DECA, which automates multi-objective Design Space Exploration using simulation, analytical models and AI-assisted optimization;
- Defacto's SoC Compiler, which automatically transforms selected architectural configurations into synthesizable RTL;
- Innova's PDM, which orchestrates design flows, computing resources and engineering data throughout the exploration process
Together, these technologies create a continuous architecture-planning flow spanning specification, exploration, implementation and design management. A user simply provides design parameters, including the ranges to explore and target KPIs, and sets priorities across power, performance, and area efficiency. From there, the platform's engine takes over autonomously: estimating area, performance (bandwidth, latency), and power across the full configuration space; identifying Pareto-optimal configurations; and automatically generating the corresponding RTL code. The result is a single, seamless flow bridging architectural exploration and design implementation.
Uniquely, SoC PLANNER assigns an eco-design footprint score to each configuration, introducing sustainability as a first-class design criterion. To our knowledge, this metric is unique in the chip design industry and can be incorporated directly into the exploration strategy.
Figure: High level SoC Planner
Validated on Real-World Use-Cases
The platform was validated on two representative industrial design scenarios covering complementary abstraction levels.
The first use-case targets the automated exploration of a configurable AI accelerator, where SoC Planner identified Pareto-optimal architectures balancing latency, power, energy consumption and silicon area, before automatically generating synthesizable RTL.
The second use-case focuses on system-level exploration of a next-generation HPC processor based on the Rhea platform. Thousands of architectural alternatives were evaluated through automated multi-objective optimization, enabling rapid identification of high-quality design trade-offs while significantly reducing exploration effort.
Across these industrial use cases, the platform demonstrated:
- up to 30–40% shorter exploration cycles;
- fully automated generation of implementation-ready RTL;
- seamless integration between architecture exploration and industrial RTL generation;
- support for sustainability-aware exploration alongside conventional PPA optimization.
By combining automated Design Space Exploration, workflow orchestration and RTL generation into a unified front-end design flow, SoC Planner establishes the foundations for a new generation of implementation-aware and sustainability-aware SoC architecture planning.
Availability
A first version of the SoC PLANNER flow is ready first users offering to design teams design exploration with aggressive PPA to generate RTL sustainability-aware design configurations.
About the Partners
Defacto Technologies: Founded in 2003, Defacto Technologies is a chip design software company providing breakthrough System-on-Chip design solutions to enhance design integration, design verification, and the Signoff of IP cores, subsystems, and large SoCs. By adopting Defacto's SoC Compiler, major semiconductor companies have moved from traditional, labor-intensive SoC design tasks to a fully automated design methodology with proven ROI across hundreds of projects.
CEA-List: CEA-List is a leading CEA technological research institute specializing in smart digital systems. Our 1,000 researchers and experts drive R&D programs, from advanced computing architectures, intelligent machines, digital instrumentation to data and systems engineering, designed to integrate AI and the digital thread into industry. By delivering disruptive technologies, we empower our industrial partners to boost their competitiveness while tackling major socio-economic challenges with a focus on human-centric and sustainable innovation. Committed to social and environmental responsibility, CEA-List has held the Institut Carnot label since 2006, reflecting our excellence in partnership-based research.
Innova Advanced Technologies: Founded in 2020 by seasoned semiconductor industry veterans, Innova's Project and Design Management (PDM) AI-based Platform is a unique EDA flow and resource management tool designed for designers and design managers of complex, multi-domain projects, from microelectronics to computer science.
This project is funded by the French state as part of the France 2030 program.
Press Contact: Defacto Technologies
