Traditionally RTL design flows are missing DFT information since many of the DFT logic is implemented and fully checked post synthesis. A typical example is the scan-based ATPG simulation with the support of compression and IEEE 1500 testing modes.
Join our exclusive webinar to discover how Defacto’s SoC Compiler enables RTL DFT simulation at different levels: IP, subsystem, and chip top. By enabling DFT simulation of ATPG vectors and DFT modes at RTL, our solution enhances the DFT signoff process pre synthesis and improves overall RTL design verification flows for complex SoC designs.
More precisely, given an RTL for a subsystem or a full chip, Defacto’s SoC Compiler enables both the generation of RTL flies with DFT and the generation of ATPG-based testbenches to let DFT and RTL designers to run DFT-based simulation fully at RTL. This enables many of the RTL DFT-based verification tasks that traditionally are considered post synthesis.
In this session, we will cover:
- How early-stage DFT verification reduces late-stage iterations and engineering costs
- Leveraging ATPG-based RTL simulation for advanced test modes
- Exploring RTL-driven test point optimizations to maximize test coverage vs. area trade-offs
- Ensuring RTL signoff of complex DFT architectures, including scan, BIST, and power intent validation.
Do not miss this opportunity to gain valuable insights on how to streamline your DFT signoff process and enhance design efficiency.
Register now and take your DFT methodology to the next level!
