Defacto SoC Compiler is a leading tool for System on Chip integration, allowing users to bring together various IP blocks such as CPU cores and interconnect fabrics according to relevant constraints and create the RTL needed to stitch all these components together. SoC Compiler is used at Arm to accelerate the generation of top-level Verilog code while reducing the scope for errors.
As an important component within key IP design flows, ensuring that SoC Compiler is able to turn around results as quickly as possible is critical to maintaining the productivity of our engineers. With that in mind, we have been reviewing the performance of the tool on the latest Arm Architecture instances available within our compute environment.
Arm performed an analysis to validate the performance of Defacto’s SoC Compiler on a spread of machines across our AWS environment.
We first looked at running SoC Compiler on its own. We used the largest instance type available for this test, to make sure that the hardware was not being shared with any other users. Here, we found that the high clock frequency R7iz instance type in AWS was about 20% faster than the Graviton3 powered R7g. However, the R7iz costs over 70% more than the R7g per vCPU hour. The R7g was faster than all the other tested instances, and at least 20% cheaper:
Figure 1. Unstressed Runtime, normalized to R7g instance type
This test allowed us to see the underlying performance of the instance types, but in real world use we would rarely have a whole CPU dedicated to a lone single-threaded task.
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Defacto’s success with bringing SoC Compiler to platforms such as AWS Graviton demonstrates the advantages of switching EDA flows to Arm Architecture compute while maintaining the same quality of tool as their customers have come to expect. The partnership between Defacto and Arm is helping to deliver tools to our joint customers that optimise the development of the next generation of Systems on Chip.
