This year Defacto will be celebrating its 20th anniversary when exhibiting at DAC in San Francisco from July the 10th to the 12th 2023 (booth #1541).
Our technical experts will be there to update you about Defacto’s SoC Compiler and in particular on the 10.0 major Release and Customer success stories.
Several customer testimonials sessions will be held every day during lunch time at our booth (please contact us to book a seat). Users from major semiconductor companies will expose how they are daily taking benefit from Defacto’s SoC Compiler capabilities to improve their overall SoC Integration process for complex SoCs.
In addition, Defacto will present new capabilities and features of its “SoC Compiler” design solution. More precisely around:
- Press-button Generation of top level RTL/IP-XACT/UPF design files for complex IP-based Subsystems given a simplified XLS specification.
- Physical assistance to help RTL designers and SoC design architects to extract area estimation and take the first back-end decisions pre-synthesis such as for feedthrough insertion pin placement for different blocks/instances, etc..
- DFT - Automatic Test Point Exploration pre-synthesis, in order to identify, the best-trade off coverage/area, by including power, clock, and physical information.
- And Many others automated SoC Design capabilities!
We look forward to meeting you in San Francisco in July!
Defacto DAC Team
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