During the past few years, we observed that SoC Design should be oriented to be seen as a commodity. A strong demand around SoC compilation is occurring in particular at front-end level. Several major semiconductor companies confirmed that the first versions of SoC should be available “at the glance”. New actors (mainly from software world) start to appear in the market and are part of such new need in terms of press button SoC generation. The strongest need is the ease of access and use of EDA tools so we keep believing that the trend from 2023 will be oriented around the cloud and even if we talk about this for now several years.
To reach such automation and accelerating the process of SoC creation requires that EDA design tools provide a much higher degree of automation to manage design information very early in the design process and at Defacto, we believe it requires a unique and new breakthrough methodology to manage unified design formats. Indeed, all design information, including functional design (RTL), architecture (IP-XACT), timing constraints (SDC), power intent (UPF), physical (LEF/DEF), must be taken into consideration together and as early as possible in the SoC build process.
In practice, such approach should allow non-domain experts to make important design decisions. For example, a CAD engineer or RTL designer would have the capability to build a first SoC configuration from design assembly to synthesis.
A complementary trend that we observe is in the design space exploration. Traditional SoC integration approaches are not sufficient anymore to forecast the best PPA design configuration, and to have smooth links between front-end and back-end teams.
Given aggressive design schedules and “low-cost” requirements, the amount of engineering resources required to run multiple what-if scenarios manually may be excessive, preventing design teams from achieving optimized solutions. The industry is looking for automated ways for SoC design planning. Learning algorithms are certainly important direction to take. Current EDA initiatives around machine learning algorithms are still timid in comparison to other industries, such as robotics and health care but seem to remain in top trends for EDA.
By Bastien Gratréaux, Project and MARCOM Lead, Defacto Technologies, published on EDACafé as part of Industry predictions.
Bastien is owner of a master’s degree in management linked to an electrical engineering background, Bastien is leading the communication at Defacto along with close interaction with R&D team for 10 years.
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About Defacto’s SoC Compiler
Defacto’s SoC Compiler is a complete SoC integration platform multi-dimensional and pre-synthesis with a high level of automation taking into consideration all the design information including RTL, IP-XACT, timing constraints, power, physical and test. Before logic synthesis, SoC Compiler enables full implementation capabilities towards IP and connectivity insertion, design editing, views generation with real time monitoring of the integration progress. This enables SoC creation in minutes and maximizes design reuse from existing projects. In addition, several APIs are provided (Tcl, Python, C++, Java, etc.) to help in the development of internal and custom design platforms.
