Due to the demand for more sophisticated applications, the design of systems-on-chip (SoC) is more and more complex. Defacto Technologies, a French provider of design solutions at Register Transfer Level (RTL) level, has released what it calls a unified SoC integration platform that automates front-end tasks and allows to make decisions early in the design flow, thus saving time and reducing costs in the design process.
“Today, we need to build SoCs quickly with a maximum of automation taking into account several dimensions: design data (RTL or gate level), power intent, electronic system design (IP-XACT), register specifications, timing constraints, interface between hardware and software,” Chouki Aktouf, CEO of Defacto Technologies, told EE Times Europe.
How to capture all these dimensions in the SoC integration phase? Defacto said it has developed a common database which is structured so that different information (e.g. RTL, gate-level, UPF, LIB) can be read and taken into account before physically building the SoC. “With SoC Compiler, our goal is to help prepare the logic synthesis and compilation phases,” said Chouki.
SoC Compiler is the ninth version of Defacto’s Star SoC integration solution.
SoC design has become a complex process requiring compartmentalization in sequential yet dependent steps. Hence the importance of unifying the design process and increasing automation.
Defacto claims SoC Compiler automates the front-end to take into consideration the physical constraints at an early stage of the design flow. For instance, Aktouf illustrated, “If I want to extract all the blocks that belong to the same power domain, I have to extract all the information related to the RTL, all the libraries that go with it and the power intent architecture that is expressed through the UPF. The solution must be able to fetch the right files, manage the consistency between the files to allow me to implement this order.”
SoC design projects almost always require customization. “If we need to add and execute custom verifications, the solution must allow them,” said Chouki. “And as soon as we make a change, it should be automatically reflected and become visible on the whole flow.”
Today, several teams, often decentralized, contribute to the SoC design project. Any update or inconsistency detection must be visible to all of them. In real time.
“If there is a consistency problem, if I can’t move this block from one level of hierarchy to another because the UPF file doesn’t exist, the tool should raise a flag,” said Chouki. SoC Compiler automatically evaluates the impact of each task on other tasks and identifies errors.
Defacto said SoC Compiler can be used with most scripting languages (Python, Perl, Tcl, etc.) and automatically translates commands into the more complex RTL code (VHDL, Verilog, System Verilog). For instance, “an engineer in India is in charge of an IP and is an expert in Tcl language,” Chouki illustrated. “Another engineer in Silicon Valley works on another block and is an expert in Python language. The platform should allow them to express themselves as they wish.” APIs are essential to a heterogeneous, multi-site team.
