We are organizing a 30mn customer presentation at the Defacto booth (#667) by Tuesday June 4th at 2:00PM.
Title: “A unified design data consistency & coherency checking solution”
Presenter: Design Manager @ TOP10 Fabless company
Summary: With the increasing complexity of design databases for large IPs & SoCs and the variety of multi-domain design standards, coherency checking between different design files for standards like RTL, UPF, Liberty, IPXACT, SDC, LEF/DEF, etc. is becoming a real challenge. On the top of Defacto’s “Build & Signoff” SoC design solution, this presentation illustrates the cost-effectiveness of an API-based checking solution that reduce significantly the coherency checks effort and also help monitoring real-time any mismatches between multi-source files.
IP Validation - Design Centric Multi-View Checks
- All checks are design centric
- RTL or gate-level design description is the golden view
- Library view is verified against design description
- Supported format: SDC, UPF, LEF, LIB
Coherency Check
- Quickly pinpoint inconsistencies
- Syntax and parsing issues
- Unmatched objects / commands
- Quality checks (clocks, constraints on hierarchical pins)
- Intuitive power-intent schematics linked with std logic design schematics
- Hierarchical of flat power-intent representation
- Power State Table visualization
- Early validation of SDC against Design
- Opportunity to fix Design or SDC
